Khvatov et al., 2022 - Google Patents
Method for Determining the Optimal Composition of a Reduced Standard Cell Library for FPGAKhvatov et al., 2022
- Document ID
- 14951621432227512252
- Author
- Khvatov V
- Zheleznikov D
- Publication year
- Publication venue
- 2022 Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)
External Links
Snippet
The number of logic functions implemented in the standard cell library for FPGA depends on the number of inputs of the LUT element. With four LUT inputs, the library contains up to 65536 cells. The number of elements in the library affects the complexity of the …
- 230000015572 biosynthetic process 0 abstract description 44
Classifications
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
- G06F17/5031—Timing analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
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- G—PHYSICS
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- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
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- G—PHYSICS
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- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
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- G—PHYSICS
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- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F17/504—Formal methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
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- G—PHYSICS
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- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
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- G—PHYSICS
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- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
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- G—PHYSICS
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- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
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- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
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