[go: up one dir, main page]

Li et al., 2013 - Google Patents

NUMA-aware algorithms: the case of data shuffling.

Li et al., 2013

View PDF
Document ID
14644577709428683445
Author
Li Y
Pandis I
Mueller R
Raman V
Lohman G
Publication year
Publication venue
CIDR

External Links

Snippet

In recent years, a new breed of non-uniform memory access (NUMA) systems has emerged: multi-socket servers of multicores. This paper makes the case that data management systems need to employ designs that take into consideration the characteristics of modern …
Continue reading at www.pandis.net (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0826—Limited pointers directories; State-only directories without pointers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Programme synchronisation; Mutual exclusion, e.g. by means of semaphores; Contention for resources among tasks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30286—Information retrieval; Database structures therefor; File system structures therefor in structured data stores
    • G06F17/30575—Replication, distribution or synchronisation of data between databases or within a distributed database; Distributed database system architectures therefor
    • G06F17/30584—Details of data partitioning, e.g. horizontal or vertical partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/80—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring

Similar Documents

Publication Publication Date Title
Li et al. NUMA-aware algorithms: the case of data shuffling.
Shukur et al. Cache coherence protocols in distributed systems
Li et al. NUMA-aware shared-memory collective communication for MPI
Maass et al. Mosaic: Processing a trillion-edge graph on a single machine
Kim et al. Multi-GPU system design with memory networks
Ziegler et al. ScaleStore: A fast and cost-efficient storage engine using DRAM, NVMe, and RDMA
Li et al. MapReduce parallel programming model: a state-of-the-art survey
US6871219B2 (en) Dynamic memory placement policies for NUMA architecture
Ramos et al. Capability models for manycore memory systems: A case-study with Xeon Phi KNL
Kissinger et al. ERIS: A NUMA-aware in-memory storage engine for analytical workloads
Zhang et al. Exploiting commutativity to reduce the cost of updates to shared data in cache-coherent systems
Ma et al. Kernel-assisted and topology-aware MPI collective communications on multicore/many-core platforms
Li et al. Improved MPI collectives for MPI processes in shared address spaces
Luo et al. Adapt: An event-based adaptive collective communication framework
Morari et al. Scaling irregular applications through data aggregation and software multithreading
Balaji et al. Combining data duplication and graph reordering to accelerate parallel graph processing
Jatala et al. A study of graph analytics for massive datasets on distributed multi-gpus
Burkhardt et al. A cloud-based approach to big graphs
Mhembere et al. knor: a NUMA-optimized in-memory, distributed and semi-external-memory k-means library
Hashmi et al. Machine-agnostic and Communication-aware Designs for MPI on Emerging Architectures
Morari et al. Efficient sorting on the Tilera manycore architecture
Asaduzzaman et al. A novel directory based hybrid cache coherence protocol for shared memory multiprocessors
Krick et al. Data management in networks: Experimental evaluation of a provably good strategy
Liu et al. Topology‐Aware Strategy for MPI‐IO Operations in Clusters
Papagiannis et al. Hybrid address spaces: A methodology for implementing scalable high-level programming models on non-coherent many-core architectures