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Ram et al., 2016 - Google Patents

Design and implementation of run time digital system using field programmable gate array–improved dynamic partial reconfiguration for efficient power consumption

Ram et al., 2016

Document ID
14587965743684258129
Author
Ram R
Marx L
Publication year
Publication venue
Journal of Computational and Theoretical Nanoscience

External Links

Snippet

In VLSI era, the recent trend evolution of transducer systems develops the structure to provide more resolution and accuracy with minimum time, area and power consumption. Reconfiguration computing is essentially driven to develop the application flexibility at run …
Continue reading at www.ingentaconnect.com (other versions)

Classifications

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    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
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    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
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