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Pomeranz et al., 1995 - Google Patents

On synthesis-for-testability of combinational logic circuits

Pomeranz et al., 1995

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Document ID
14232227314258020572
Author
Pomeranz I
Reddy S
Publication year
Publication venue
Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

External Links

Snippet

We propose a synthesis method that modifies a given circuit to reduce the number of gates and the number of paths in the circuit. The synthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. Comparison units are …
Continue reading at dl.acm.org (PDF) (other versions)

Classifications

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    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
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    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • GPHYSICS
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    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30Marginal testing, e.g. varying supply voltage

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