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Tsikhanovich et al., 2005 - Google Patents

A methodology for HW/SW specification and simulation at multiple levels of abstraction

Tsikhanovich et al., 2005

Document ID
14122352962145317219
Author
Tsikhanovich A
Aboulhamid E
Bois G
Publication year
Publication venue
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

External Links

Snippet

In this paper we propose a new specification and simulation modeling methodology that supports the application of transactional level modeling in the design cycle of hardware/software (HW/SW) systems allowing the exploration and validation of design …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/504—Formal methods
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    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
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    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
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    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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    • G06F11/00—Error detection; Error correction; Monitoring

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