Cho et al., 2009 - Google Patents
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routabilityCho et al., 2009
View PDF- Document ID
- 14082108178124605191
- Author
- Cho M
- Lu K
- Yuan K
- Pan D
- Publication year
- Publication venue
- ACM Transactions on Design Automation of Electronic Systems (TODAES)
External Links
Snippet
In this article, we present BoxRouter 2.0, and discuss its architecture and implementation. As high-performance VLSI design becomes more interconnect-dominant, efficient congestion elimination in global routing is in greater demand. Hence, we propose a global router which …
- 230000000750 progressive 0 abstract description 11
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5077—Routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/12—Design for manufacturability
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/82—Noise analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Cho et al. | BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability | |
| Cho et al. | BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router | |
| Pan et al. | FastRoute: A step to integrate global routing into placement | |
| Chang et al. | NTHU-Route 2.0: a robust global router for modern designs | |
| JP2009087376A (en) | Method and apparatus for interconnection | |
| Chang et al. | Physical hierarchy generation with routing congestion control | |
| Ao et al. | Delay-driven layer assignment in global routing under multi-tier interconnect structure | |
| Wang et al. | Multi-center congestion estimation and minimization during placement | |
| Nam et al. | The ISPD global routing benchmark suite | |
| Zhou et al. | Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors | |
| Li et al. | Guiding a physical design closure system to produce easier-to-route designs with more predictable timing | |
| Ozdal et al. | Archer: A history-based global routing algorithm | |
| Kong et al. | Automatic bus planner for dense PCBs | |
| He et al. | Ripple 2.0: Improved movement of cells in routability-driven placement | |
| Shelar | An efficent clustering algorithm for low power clock tree synthesis | |
| Cong et al. | Buffer block planning for interconnect planning and prediction | |
| Yu et al. | TILA: Timing-driven incremental layer assignment | |
| Moffitt | Global routing revisited | |
| Shelar et al. | A predictive distributed congestion metric and its application to technology mapping | |
| Ma et al. | Dynamic global buffer planning optimization based on detail block locating and congestion analysis | |
| Zuber et al. | Wire topology optimization for low power CMOS | |
| Chow et al. | Placement: from wirelength to detailed routability | |
| Mo et al. | Fishbone: a block-level placement and routing scheme | |
| Jiang et al. | Simultaneous floorplanning and buffer block planning | |
| Hyun et al. | Airgap Insertion and Layer Reassignment Under Setup and Hold Timing Constraints |