[go: up one dir, main page]

Gupta et al., 2015 - Google Patents

Efficient bus arbitration protocol for SoC design

Gupta et al., 2015

Document ID
14042225818779275340
Author
Gupta J
Goel N
Publication year
Publication venue
2015 International Conference on Smart Technologies and Management for Computing, Communication, Controls, Energy and Materials (ICSTM)

External Links

Snippet

Improvement in the electronic devices and IC technologies has led to the need of fast arbiter design and encouragement of SoC design. Thus, an arbiter is required that matches with the SoC design speed. This paper presents a configurable arbiter for n users. The proposed …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled

Similar Documents

Publication Publication Date Title
Lahiri et al. LOTTERYBUS: A new high-performance communication architecture for system-on-chip designs
US11403221B2 (en) Memory access response merging in a memory hierarchy
Daneshtalab et al. Memory-efficient on-chip network with adaptive interfaces
CN101383712A (en) A Routing Node Microstructure of Network-on-Chip
Gupta et al. Efficient bus arbitration protocol for SoC design
Shrivastava et al. Various arbitration algorithm for on-chip (AMBA) shared bus multi-processor SoC
US6700899B1 (en) Bit slice arbiter
Hoornaert et al. A memory scheduling infrastructure for multi-core systems with re-programmable logic
Jeong et al. REACT: Scalable and high-performance regular expression pattern matching accelerator for in-storage processing
Bashizade et al. P2R2: Parallel pseudo-round-robin arbiter for high performance NoCs
Zhang et al. A multi-VC dynamically shared buffer with prefetch for network on chip
CN104346303A (en) Bus arbitration method and device
Park et al. Adaptively weighted round‐robin arbitration for equality of service in a many‐core network‐on‐chip
Pyoun et al. The efficient bus arbitration scheme in SoC environment
Liu et al. A dynamic adaptive arbiter for Network-on-Chip
El-Kustaban et al. A Bus Arbitration Scheme with an Efficient Utilization and Distribution
Tiwari et al. Comparative analysis of different lottery bus arbitration techniques for SoC communication
Huang et al. Service-oriented architecture design for virtualization in network-on-chip
US6732199B1 (en) Software programmable calendar queue cache
US7130947B2 (en) Method of arbitration which allows requestors from multiple frequency domains
Monemi et al. An enhanced dynamic weighted incremental technique for QoS support in NoC
Kapre Hoplite-Q: Priority-aware routing in FPGA overlay NoCs
Bajaj et al. Arbitration schemes for multiprocessor Shared Bus
Paul et al. Reconfigurable parallel architecture of high speed round robin arbiter
Venkataraman et al. Design of Matrix Distributive Round Robin Ping Pong and Enhanced Ping Lock Arbiter for Shared Resource Systems