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Wolf, 2021 - Google Patents

Yosys manual

Wolf, 2021

View PDF
Document ID
13486735310455699631
Author
Wolf C
Publication year
Publication venue
Retrieved January

External Links

Snippet

Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools. In special cases such as synthesis for coarse-grain cell libraries or when testing new synthesis algorithms it might be necessary to write a custom HDL …
Continue reading at yosyshq.net (PDF) (other versions)

Classifications

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    • G06F17/5009—Computer-aided design using simulation
    • G06F17/504—Formal methods
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    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
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    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
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