Yenimol, 2022 - Google Patents
Hardware/software co-design of domain-specific risc-v processor for graph applicationsYenimol, 2022
View PDF- Document ID
- 1333245848389778405
- Author
- Yenimol M
- Publication year
- Publication venue
- PQDT-Global
External Links
Snippet
Graph applications are employed in many fields but show poor performance on general- purpose computing systems due to heavy, irregular, and data-driven memory access patterns. The diverse topology of real-life graphs also affects the performance. Even though …
- 230000000903 blocking 0 abstract description 2
Classifications
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- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
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- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
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- G—PHYSICS
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- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result; Formation of operand address; Addressing modes
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- G—PHYSICS
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- G06F17/5045—Circuit design
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- G06F9/46—Multiprogramming arrangements
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- G—PHYSICS
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