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Solay et al., 2021 - Google Patents

Design and analysis of gate engineered gate-AII-Around (GAA) charge plasma nanowire field effect transistor

Solay et al., 2021

Document ID
13161388779391834989
Author
Solay L
Kumar P
Amin I
Anand S
Publication year
Publication venue
2021 6th international conference for convergence in technology (I2CT)

External Links

Snippet

The reported work shows the effect of gate engineering techniques upon Gate All Around (GAA)-Charge Plasma (CP)-Nanowire FET. The proposed architecture includes both dual material gate (DMG) and Gate stacking (GS) techniques making it a GAA-Dual Material Gate …
Continue reading at ieeexplore.ieee.org (other versions)

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