Reynolds et al., 2019 - Google Patents
Refutation-based synthesis in smtReynolds et al., 2019
View PDF- Document ID
- 12844987302077224518
- Author
- Reynolds A
- Kuncak V
- Tinelli C
- Barrett C
- Deters M
- Publication year
- Publication venue
- Formal methods in system design
External Links
Snippet
We introduce the first program synthesis engine implemented inside an SMT solver. We present an approach that extracts solution functions from unsatisfiability proofs of the negated form of synthesis conjectures. We also discuss novel counterexample-guided …
- 230000002194 synthesizing 0 title abstract description 128
Classifications
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- G06F8/40—Transformations of program code
- G06F8/41—Compilation
- G06F8/43—Checking; Contextual analysis
- G06F8/436—Semantic checking
- G06F8/437—Type checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F11/00—Error detection; Error correction; Monitoring
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- G06F11/3604—Software analysis for verifying properties of programs
- G06F11/3608—Software analysis for verifying properties of programs using formal methods, e.g. model checking, abstract interpretation
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- G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
- G06F8/451—Code distribution
- G06F8/452—Loops
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- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/44—Arrangements for executing specific programmes
- G06F9/445—Programme loading or initiating
- G06F9/44589—Programme code verification, e.g. Java bytecode verification, proof-carrying code
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