C. Penha et al., 2019 - Google Patents
ADD: Accelerator Design and Deploy‐A tool for FPGA high‐performance dataflow computingC. Penha et al., 2019
- Document ID
- 12691221922347562640
- Author
- C. Penha J
- B. Silva L
- M. Silva J
- Coelho K
- P. Baranda H
- M. Nacif J
- S. Ferreira R
- Publication year
- Publication venue
- Concurrency and Computation: Practice and Experience
External Links
Snippet
Dataflow‐based FPGA accelerators have become a promising alternative to deliver energy‐ efficient high‐performance computing. However, FPGA programming is still a challenge. This paper presents Accelerator Design and Deploy (ADD), a high‐level framework to …
- 238000004088 simulation 0 abstract description 25
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
- G06F8/41—Compilation
- G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/44—Arrangements for executing specific programmes
- G06F9/455—Emulation; Software simulation, i.e. virtualisation or emulation of application or operating system execution engines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN109213523B (en) | Processor, method and system for configurable spatial accelerator with memory system performance, power reduction and atomic support features | |
Windh et al. | High-level language tools for reconfigurable computing | |
Liu et al. | OverGen: Improving FPGA usability through domain-specific overlay generation | |
US20030074177A1 (en) | System, method and article of manufacture for a simulator plug-in for co-simulation purposes | |
US20030033588A1 (en) | System, method and article of manufacture for using a library map to create and maintain IP cores effectively | |
US20030046668A1 (en) | System, method and article of manufacture for distributing IP cores | |
Zhang et al. | Graphagile: An fpga-based overlay accelerator for low-latency gnn inference | |
CN112148647A (en) | Apparatus, method and system for memory interface circuit arbitration | |
De Haro et al. | OmpSs@ FPGA framework for high performance FPGA computing | |
Angepat et al. | FPGA-accelerated simulation of computer systems | |
Leow et al. | Generating hardware from OpenMP programs | |
C. Penha et al. | ADD: Accelerator Design and Deploy‐A tool for FPGA high‐performance dataflow computing | |
Kapre et al. | Survey of domain-specific languages for FPGA computing | |
Matthews et al. | MosaicSim: A lightweight, modular simulator for heterogeneous systems | |
Bo et al. | Automata processing in reconfigurable architectures: In-the-cloud deployment, cross-platform evaluation, and fast symbol-only reconfiguration | |
Verdoscia et al. | A Data‐Flow Soft‐Core Processor for Accelerating Scientific Calculation on FPGAs | |
Ya. Steinberg et al. | Automatic high-level programs mapping onto programmable architectures | |
Biancolin et al. | Accessible, FPGA resource-optimized simulation of multiclock systems in firesim | |
Klaisoongnoen et al. | Evaluating Versal AI Engines for option price discovery in market risk analysis | |
Caldeira et al. | From java to fpga: an experience with the intel harp system | |
Ashworth et al. | First steps in porting the lfric weather and climate model to the fpgas of the euroexa architecture | |
Bragança et al. | Simplifying HW/SW integration to deploy multiple accelerators for CPU-FPGA heterogeneous platforms | |
Qadri et al. | Multicore Technology: Architecture, Reconfiguration, and Modeling | |
Svensson | Occam‐pi for Programming of Massively Parallel Reconfigurable Architectures | |
Nguyen et al. | Design and implementation of a coarse-grained dynamically reconfigurable multimedia accelerator |