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Beyls et al., 2004 - Google Patents

Platform-independent cache optimization by pinpointing low-locality reuse

Beyls et al., 2004

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Document ID
12572613636190164555
Author
Beyls K
D’Hollander E
Publication year
Publication venue
International Conference On Computational Science

External Links

Snippet

For many applications, cache misses are the primary performance bottleneck. Even though much research has been performed on automatically optimizing cache behavior at the hardware and the compiler level, many program executions remain dominated by cache …
Continue reading at core.ac.uk (PDF) (other versions)

Classifications

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    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3842—Speculative instruction execution
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    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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    • G—PHYSICS
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