Yang et al., 2007 - Google Patents
Automating logic rectification by approximate SPFDsYang et al., 2007
View HTML- Document ID
- 12390418200281400516
- Author
- Yang Y
- Sinha S
- Veneris A
- Brayton R
- Publication year
- Publication venue
- 2007 Asia and South Pacific Design Automation Conference
External Links
Snippet
In the digital VLSI cycle, a netlist is often modified to correct design errors, perform small specification changes or implement incremental rewiring-based optimization operations. Most existing automated logic rectification tools use a small set of predefined logic …
- 230000001131 transforming 0 abstract description 28
Classifications
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- G06F17/5009—Computer-aided design using simulation
- G06F17/504—Formal methods
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- G—PHYSICS
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- G06F17/50—Computer-aided design
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- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
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- G06F17/5022—Logic simulation, e.g. for logic circuit operation
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- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
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