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Pai et al., 1999 - Google Patents

Code transformations to improve memory parallelism

Pai et al., 1999

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Document ID
12282192778107468190
Author
Pai V
Adve S
Publication year
Publication venue
MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture

External Links

Snippet

Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in removing memory stall time than CPU time, making the memory system a greater bottleneck in ILP …
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Classifications

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    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
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    • G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
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