[go: up one dir, main page]

Tiwari - Google Patents

Performance Evaluation of NOC Router Architecture by Using VHDL

Tiwari

View PDF
Document ID
12249973111430101348
Author
Tiwari V

External Links

Snippet

Present day technology for ASICs supports Networks-on-Chip designs which can have 100 million gates on a single chip. The latest FPGAs can support only about 10 million gates to accommodate all logic and the associated routing. In order to implement a competitive NoC …
Continue reading at www.ijerct.com (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding through a switch fabric
    • H04L49/253—Connections establishment or release between ports
    • H04L49/254—Centralized controller, i.e. arbitration or scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Switching fabric construction
    • H04L49/101—Crossbar or matrix
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Switching fabric construction
    • H04L49/109—Switching fabric construction integrated on microchip, e.g. switch-on-chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/80—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection; Overload protection
    • H04L49/505—Corrective Measures, e.g. backpressure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3027—Output queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/40—Wormhole routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Application specific switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/60—Router architecture
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems
    • H04L12/56—Packet switching systems

Similar Documents

Publication Publication Date Title
Sethuraman et al. LiPaR: A light-weight parallel router for FPGA-based networks-on-chip
US10911352B2 (en) Multicast message delivery using a directional two-dimensional router and network
Panades et al. A low cost network-on-chip with guaranteed service well suited to the GALS approach
CN109376118B (en) Programmable Logic Devices with On-Chip Integrated Networks
Bartic et al. Highly scalable network on chip for reconfigurable systems
EP3298740A1 (en) Directional two-dimensional router and interconnection network for field programmable gate arrays, and other circuits, and applications of the router and network
Pande et al. High-throughput switch-based interconnect for future SoCs
Abdallah et al. Basic network-on-chip interconnection for future gigascale MCSoCs applications: Communication and computation orthogonalization
Pionteck et al. Communication architectures for dynamically reconfigurable FPGA designs
Tiwari Performance Evaluation of NOC Router Architecture by Using VHDL
Anjali et al. Design and evaluation of virtual channel router for mesh-of-grid based NoC
Lee et al. Design of a feasible on-chip interconnection network for a chip multiprocessor (cmp)
Seifi et al. A clustered NoC in group communication
Chemli et al. Architecture and performances comparison of Network on chip router for hierarchical mesh topology
Samanth et al. Design and analysis of four port router for network-on-chip applications
Dananjayan et al. Low Latency NoC Switch using Modified Distributed Round Robin Arbiter.
Seifi et al. Clustered NOC, a suitable design for group communications in Network on Chip
Saastamoinen et al. Interconnect IP for gigascale system-on-chip
Jara-Berrocal et al. SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems
Sharma et al. Performance of router design for Network-on-Chip implementation
Alimi et al. Network-on-Chip Topologies: Potentials, Technical Challenges
Sun et al. Design and implementation of the wormhole virtual channel NoC router
George DESIGN AND FPGA IMPLEMENTATION OF A ROUTER FOR NoC
Kumar et al. Parallel Distributed Round Robin Arbiter for Network on Chip
Nishi et al. The JUMP-1 Router Chip: A versatile router for supporting a distributed shared memory