Xu et al., 2024 - Google Patents
Pie: Pooling cpu memory for llm inferenceXu et al., 2024
View PDF- Document ID
- 10967260677380658667
- Author
- Xu Y
- Mao Z
- Mo X
- Liu S
- Stoica I
- Publication year
- Publication venue
- arXiv preprint arXiv:2411.09317
External Links
Snippet
The rapid growth of LLMs has revolutionized natural language processing and AI analysis, but their increasing size and memory demands present significant challenges. A common solution is to spill over to CPU memory; however, traditional GPU-CPU memory swapping …
- 230000015654 memory 0 title abstract description 176
Classifications
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- G06F9/46—Multiprogramming arrangements
- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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- G—PHYSICS
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
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- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
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