Hameed et al., 2018 - Google Patents
Performance and energy-efficient design of STT-RAM last-level cacheHameed et al., 2018
View PDF- Document ID
- 10819720781537144234
- Author
- Hameed F
- Khan A
- Castrillon J
- Publication year
- Publication venue
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
External Links
Snippet
Recent research has proposed having a die-stacked last-level cache (LLC) to overcome the memory wall. Lately, spin-transfer-torque random access memory (STT-RAM) caches have received attention, since they provide improved energy efficiency compared with DRAM …
- 230000015654 memory 0 abstract description 64
Classifications
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