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Taito et al., 2003 - Google Patents

An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write

Taito et al., 2003

Document ID
10297802154853415588
Author
Taito Y
Tanizaki T
Kinoshita M
Igaue F
Fujino T
Arimoto K
Publication year
Publication venue
IEEE Journal of Solid-State Circuits

External Links

Snippet

This paper describes a 4-Mb embedded DRAM macro using novel fast random cycle architecture with sense-synchronized read/write (SSR/SSW). The test chip has been fabricated with a 0.15-μm logic-based embedded DRAM process and the 1.5-V 143-MHz no …
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Classifications

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