Silva et al., 2018 - Google Patents
A distributed functional verification environment for the design of system-on-chip in heterogeneous architecturesSilva et al., 2018
- Document ID
- 10073489667297205665
- Author
- Silva T
- Morais D
- Andrade H
- Nunes F
- Melcher E
- Lima A
- Brito A
- Publication year
- Publication venue
- 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)
External Links
Snippet
In complex System-on-a-Chip (SoC) projects, the conclusion of the project depends on the functional verification phase, which takes a long time. Synchronizing distributed and heterogeneous components in a functional verification environment might not be a simple …
- 238000000034 method 0 abstract description 15
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/86—Hardware-Software co-design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Mehta | ASIC/SoC functional design verification | |
US9064068B1 (en) | Debuggable opaque IP | |
KR100491461B1 (en) | METHOD AND APPARATUS FOR SoC DESIGN VALIDATION | |
US9703579B2 (en) | Debug environment for a multi user hardware assisted verification system | |
US10664563B2 (en) | Concurrent testbench and software driven verification | |
JP2007164780A (en) | Method, system, and program (method and system of design verification) | |
US10949589B2 (en) | Method for compression of emulation time line in presence of dynamic re-programming of clocks | |
CN112673376A (en) | Hardware emulation system and method for identifying state-retaining loops and oscillating loops | |
US10664637B2 (en) | Testbench restoration based on capture and replay | |
Silva et al. | A distributed functional verification environment for the design of system-on-chip in heterogeneous architectures | |
Ke et al. | Verification of AMBA bus model using SystemVerilog | |
Jain et al. | Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator | |
US20040153301A1 (en) | Integrated circuit development methodology | |
Kaith et al. | A technical road map from system verilog to UVM | |
Amruth et al. | Five Stage Pipelined MIPS Processor Verification Scoreboard Module using UVM | |
Lund | Design and Application of a Co-Simulation Framework for Chisel | |
Jain et al. | Unified and Modular Modeling and Functional Verification Framework of Real‐Time Image Signal Processors | |
CN112818627A (en) | More efficient/useful electronic structure for circuit design, test and/or fabrication | |
CN118504478B (en) | Method, electronic device and storage medium for designing simulation logic system | |
Patel et al. | Transaction-based debug of PCI Express embedded SoC platforms | |
Siddiqui | System-on-Chip (SoC) emulation | |
ANAND | RTL DESIGN AND UVM RAL VERIFICATION OF AMBA–APB PROTOCOL | |
Kurula | A FRAMEWORK FOR EARLY SYSTEM-ON-CHIP CO-VALIDATION | |
US20130311966A1 (en) | Circuit design support apparatus, computer-readable recording medium, and circuit design support method | |
Djemal et al. | A novel formal verification approach for RTL hardware IP cores |