Arundeepakvel et al., 2019 - Google Patents
Realization of memristor based D-latchArundeepakvel et al., 2019
- Document ID
- 10040098778035771264
- Author
- Arundeepakvel R
- Khatter P
- Pandey N
- et al.
- Publication year
- Publication venue
- 2019 International Conference on Computing, Power and Communication Technologies (GUCON)
External Links
Snippet
Latches and flip-flops are the basic unit in digital systems and for almost all sequential circuits. They preserve their state in the absence of the clock signal and hence store information as 0s (low voltage level) and 1s (high voltage level). This paper presents a novel …
- 238000004088 simulation 0 abstract description 11
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Wang et al. | High-density memristor-CMOS ternary logic family | |
| Liu et al. | A carry lookahead adder based on hybrid CMOS-memristor logic circuit | |
| Kvatinsky et al. | MRL—Memristor ratioed logic | |
| Singh | Hybrid memristor-cmos (memos) based logic gates and adder circuits | |
| CN106941350B (en) | A memristor-based XOR gate circuit and design and fabrication method | |
| Rajendran et al. | Memristor based programmable threshold logic array | |
| Teimoori et al. | A novel hybrid CMOS-memristor logic circuit using Memristor Ratioed Logic | |
| Elgabra et al. | Mathematical modeling of a memristor device | |
| Zheng et al. | Memristor-based nonvolatile synchronous flip-flop circuits | |
| Chakraborty et al. | Design of memristor-based up-down counter using material implication logic | |
| Sasi et al. | Hybrid memristor-CMOS based linear feedback shift register design | |
| Maan et al. | Voltage controlled memristor threshold logic gates | |
| Arundeepakvel et al. | Realization of memristor based D-latch | |
| Wang et al. | An improved memristor-CMOS XOR logic gate and a novel full adder | |
| US9742403B2 (en) | State-retaining logic cell | |
| Ibrahim et al. | Digital design using CMOS and hybrid CMOS/memristor gates: A comparative study | |
| CN112332813B (en) | A CMOS Hybrid Edge Memristor D Flip-Flop Circuit with Asynchronous Set-Reset | |
| Amrani et al. | Logic design with unipolar memristors | |
| Dhongade et al. | Design and analysis of memristor-CMOS based hybrid D latch | |
| Mozafari et al. | A Novel Architecture for Memristor-Based Logic | |
| Sushma et al. | Low power high speed D flip flop design using improved SVL technique | |
| Mbarek et al. | Design and analysis of nonvolatile memristor-based SR Latch | |
| Singh | Power and area efficient hybrid memristor-CMOS based 2’s complement fsm for high-performance computing system | |
| Kumar et al. | Design of digital functional blocks using hybrid memristor structures | |
| Priyanka et al. | An efficient prompt multiplexers using memristor |