Swetha et al., 2025 - Google Patents
Design and Analysis of Low Power and High Speed 8-Bit ALU Using Hybrid Full AdderSwetha et al., 2025
- Document ID
- 9751203338826337356
- Author
- Swetha S
- Akhila B
- Harshitha Y
- Varma Y
- Publication year
- Publication venue
- 2025 9th International Conference on Inventive Systems and Control (ICISC)
External Links
Snippet
This work uses an optimized Modified Gate Diffusion Input (MGDI) technique to design a low- power, high-speed, 8-bit Arithmetic Logic Unit (ALU) that is implemented in 90 nm CMOS technology. The suggested ALU uses a hybrid full adder based on XOR and MUX logic to …
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Zimmermann et al. | Low-power logic styles: CMOS versus pass-transistor logic | |
| Vallabhuni et al. | Comparative Analysis of 8-Bit Manchester Carry Chain Adder Using FinFET at 18nm Technology | |
| Juma et al. | Multiplier Design using Machine Learning Alogorithms for Energy Efficiency | |
| Sarkar et al. | 8-bit ALU design using m-GDI technique | |
| Nigam et al. | Comparative Analysis of 28T Full adder with 14T Full adder using 180nm | |
| Anand et al. | A low power and high speed 8-bit ALU design using 17T full adder | |
| Kishore et al. | Low power and high speed optimized 4-bit array multiplier using MOD-GDI technique | |
| Swetha et al. | Design and Analysis of Low Power and High Speed 8-Bit ALU Using Hybrid Full Adder | |
| Swetha et al. | Low-power MIPS 32-bit ALU: A MGDI-FS technique with 90 nm technology | |
| Biswas et al. | A 2.319 uw, 37.34 MHz transmission gate based 4-bit ALU for contemporary low-powered, high-speed microprocessors | |
| Vardhan et al. | Design and implementation of low power nand gate based combinational circuits using finfet technique | |
| Kandpal et al. | A hybrid fa for high performance arithmetic application | |
| Kumar et al. | A Study and Analysis of High Speed Adders in Power-Constrained Environment | |
| Ramanathan et al. | A novel power delay optimized 32-bit parallel prefix adder for high speed computing | |
| Swathi et al. | Electronic device performance enhancement through low-power, high-speed IC design with GDI-based carry look-ahead adders | |
| Bhuvaneshwari et al. | Low Power CMOS GDI Full-adder Design | |
| Basha et al. | Exploring energy efficient area optimized one-bit full Subtractor circuit for Signal processing application using CMOS and FinFET Technology | |
| Chakraborty et al. | Design of a Digital Full Adder Circuit in 16 nm FinFET Process | |
| Kusumanchi et al. | Design and Optimization of a Hybrid ALU Using CMOS, Pass Transistor Logic, and Transmission Gate Logic for Low-Power Applications | |
| Mishra et al. | On the design of high-performance CMOS 1-bit full adder circuits | |
| Kalavathidevi et al. | FPGA Implementation and Optimization of Adder Performance with Hybrid FinFET-GDI Logic | |
| Kattepogu et al. | Low Power High Speed Modified GDI Full Adder Implemented by NCFET Technologies | |
| Garg et al. | Design and Implementation of Low Power Energy Efficient 14T Hybrid Full Adder for Multiplier Applications | |
| Sahu et al. | Low Power ALU Design and Implementation Using Clock Gating and Carry Select Adder | |
| Shrivathsa et al. | Survey on high speed low power full adder circuits |