Darwish et al., 2020 - Google Patents
Transaction-Level Power ModelingDarwish et al., 2020
- Document ID
- 9730121999474520469
- Author
- Darwish A
- El-Moursy M
- Dessouky M
- Publication year
External Links
Snippet
Transaction-Level Modeling (TLM) is a technique for building and developing designs. TLM introduces abstract modeling of communication schemes between design modules. It provides insights for system-level design at early stages of development. Thus, TLM …
- 238000000034 method 0 abstract description 202
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
- G06F17/5031—Timing analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/504—Formal methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3636—Software debugging by tracing the execution of the program
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/86—Hardware-Software co-design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/68—Processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Izraelevitz et al. | Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations | |
Mehta | ASIC/SoC functional design verification | |
Rogers et al. | gem5-salam: A system architecture for llvm-based accelerator modeling | |
Chen et al. | System-level validation: high-level modeling and directed test generation techniques | |
Kambe et al. | A c-based synthesis system, bach, and its application (invited talk) | |
Whatmough et al. | CHIPKIT: An agile, reusable open-source framework for rapid test chip development | |
Renaudin et al. | A design framework for asynchronous/synchronous circuits based on CHP to HDL translation | |
Villarraga et al. | Software in a Hardware View: New Models for HW-dependent Software in SoC Verification | |
Ebeid et al. | HDL code generation from UML/MARTE sequence diagrams for verification and synthesis | |
Biancolin et al. | Accessible, FPGA resource-optimized simulation of multiclock systems in firesim | |
Gong et al. | Functional verification of dynamically reconfigurable FPGA-based systems | |
Bailey et al. | Tlm-driven design and verification methodology | |
Khan et al. | GHAZI: An open-source ASIC implementation of RISC-V based SoC | |
Schliebusch et al. | A framework for automated and optimized ASIP implementation supporting multiple hardware description languages | |
Ahuja et al. | Low Power Design with High-Level Power Estimation and Power-Aware Synthesis | |
Darwish et al. | Transaction-Level Power Modeling | |
Kambe et al. | Trend of system level design and an approach to C-based design | |
Ahuja | High level power estimation and reduction techniques for power aware hardware design | |
Nepomnyashchy et al. | High-Level design flows for VLSI circuit | |
Nataraja | A Research-Fertile Co-Emulation Framework for RISC-V Processor Verification | |
Mrad et al. | A framework for system level low power design space exploration | |
Magyar | Improving FPGA Simulation Capacity with Automatic Resource Multi-Threading | |
Darwish et al. | Transaction-Level Power Modeling Methodology | |
Chattopadhyay et al. | Architecture Description Languages | |
Ruelas-Petrisko | A Qualitative Approach to Agile Hardware Design |