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Jiang et al., 2004 - Google Patents

Macro-models for high level area and power estimation on FPGAs

Jiang et al., 2004

Document ID
9429588555892534750
Author
Jiang T
Tang X
Banerjee P
Publication year
Publication venue
Proceedings of the 14th ACM Great Lakes symposium on VLSI

External Links

Snippet

As more and more complex applications are implemented on FPGAs, high-level design tools are needed to reduce the design time. A good high-level synthesis tool usually has an automated design space exploration pass to determine the effects of various compiler …
Continue reading at dl.acm.org (other versions)

Classifications

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