Sullivan et al., 2018 - Google Patents
Swapcodes: Error codes for hardware-software cooperative gpu pipeline error detectionSullivan et al., 2018
View PDF- Document ID
- 8357619086102331678
- Author
- Sullivan M
- Hari S
- Zimmer B
- Tsai T
- Keckler S
- Publication year
- Publication venue
- 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
External Links
Snippet
Intra-thread instruction duplication offers straightforward and effective pipeline error detection for data-intensive processors. However, software-enforced instruction duplication uses explicit checking instructions, roughly doubles program register usage, and doubles …
- 238000001514 detection method 0 title abstract description 36
Classifications
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- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
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