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Burtscher et al., 2002 - Google Patents

Hybrid load-value predictors

Burtscher et al., 2002

Document ID
7706395143062497165
Author
Burtscher M
Zorn B
Publication year
Publication venue
IEEE Transactions on Computers

External Links

Snippet

Load instructions diminish processor performance in two ways. First, due to the continuously widening gap between CPU and memory speed, the relative latency of load instructions grows constantly and the slows program execution. Next, memory reads limit the available …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
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