Comisky et al., 2000 - Google Patents

Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
  • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
  • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
  • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
  • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
  • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
  • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/40—Bus structure
  • G06F13/4004—Coupling between buses
  • G06F13/4027—Coupling between buses using bus bridges
  • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/76—Architectures of general purpose stored programme computers
  • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for programme control, e.g. control unit
  • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
  • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for programme control, e.g. control unit
  • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
  • G06F9/46—Multiprogramming arrangements
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/10—Programme control for peripheral devices
  • G06F13/12—Programme control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
  • G06F13/124—Programme control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
  • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
  • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers
  • G06F3/0601—Dedicated interfaces to storage systems
  • G06F3/0602—Dedicated interfaces to storage systems specifically adapted to achieve a particular effect
  • G06F3/061—Improving I/O performance

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