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Kredo et al., 2019 - Google Patents

Toward Automated Simulink Model Implementation and Optimization using High-Level Synthesis for FPGA

Kredo et al., 2019

Document ID
6806975151314978761
Author
Kredo K
Mustafa H
Crosbie R
Bednar R
Alavi Z
Publication year
Publication venue
2019 IEEE Electric Ship Technologies Symposium (ESTS)

External Links

Snippet

FPGAs have shown great potential in accelerating the execution of a wide variety of workloads, including simulations of physical and electrical systems. However, many users do not possess sufficient expertise in modern digital design techniques to achieve the …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
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    • G06F8/44—Encoding
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    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
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    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. incrementing the instruction counter, jump
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