Kobenge et al., 2009 - Google Patents
A power efficient digitally programmable delay element for low power VLSI applicationsKobenge et al., 2009
View PDF- Document ID
- 668840500657185418
- Author
- Kobenge S
- Yang H
- Publication year
- Publication venue
- 2009 1st Asia Symposium on Quality Electronic Design
External Links
Snippet
Digitally programmable delay elements (DPDE) are required to be monotonic and low power. In this paper, a low power digitally programmable delay element (DPDE) with monotonic delay characteristics is proposed. A dynamic current mirror together with a …
- 230000003068 static 0 abstract description 11
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Abdulrazzaq et al. | A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance | |
| Maymandi-Nejad et al. | A digitally programmable delay element: design and analysis | |
| Mandal et al. | Ring oscillators: Characteristics and applications | |
| Deng et al. | A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection technique | |
| Su et al. | A low-jitter cell-based digitally controlled oscillator with differential multiphase outputs | |
| Moon et al. | Monotonic wide-range digitally controlled oscillator compensated for supply voltage variation | |
| Singhvi et al. | A fine-grained, uniform, energy-efficient delay element for FD-SOI technologies | |
| Sahani et al. | A wide frequency range low jitter integer PLL with switch and inverter based CP in 0.18 μ m CMOS technology | |
| Kobenge et al. | A power efficient digitally programmable delay element for low power VLSI applications | |
| US20060284693A1 (en) | Digitally controlled oscillator for reduced power over process variations | |
| Elrabaa | A portable high-frequency digitally controlled oscillator (DCO) | |
| Gorji et al. | A 2.7 to 4.6 GHz multi-phase high resolution and wide tuning range digitally-controlled oscillator in CMOS 65nm | |
| Dabas et al. | A new design of digitally controlled oscillator for low power applications | |
| Kumar et al. | Digitally controlled oscillator design with a variable capacitance XOR gate | |
| Chang et al. | A low-jitter ADPLL with adaptive high-order loop filter and fine grain varactor based DCO | |
| Dabas et al. | A CMOS based low power digitally controlled oscillator design with MOS varactor | |
| Ou et al. | Phase noise simulation and estimation methods: A comparative study | |
| Liu et al. | Accurate performance evaluation of jitter-power FOM for multiplying delay-locked loop | |
| Wei et al. | Novel building blocks for PLL using complementary logic in 28nm UTBB-FDSOI technology | |
| Majd et al. | An ultra-low-power 15-bit digitally controlled oscillator with high resolution | |
| Jayasudha et al. | A Monotonic Digitally Programmable Delay Element for Low Power VLSI Applications | |
| Sheng et al. | A monotonic and low-power digitally controlled oscillator using standard cells for SoC applications | |
| Esmaeilzadeh et al. | A wide-range low-power thyristor-based delay element with improved temperature sensitivity | |
| Chakraborty et al. | Design and Analysis of an Area and Power Efficient Programmable Delay Cell | |
| Manjunath et al. | A low-power low-voltage CMOS thyristor based delay element |