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Tehrani et al., 2000 - Google Patents

Deep sub-micron static timing analysis in presence of crosstalk

Tehrani et al., 2000

Document ID
628940468254928002
Author
Tehrani P
Chyou S
Ekambaram U
Publication year
Publication venue
Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)

External Links

Snippet

A complete and accurate method for static timing analysis of deep sub-micron devices in presence of crosstalk is introduced. This scheme provides an efficient platform for fast and accurate static timing verification of large scale transistor and cell level netlists, with coupled …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G06F17/5031—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
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