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Bruguera, 2018 - Google Patents

Radix-64 floating-point divider

Bruguera, 2018

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Document ID
6229712127957780451
Author
Bruguera J
Publication year
Publication venue
2018 IEEE 25th Symposium on Computer Arithmetic (ARITH)

External Links

Snippet

Radix-64 Floating-Point Divider Page 1 Radix-64 Floating-Point Divider Javier D. Bruguera ARM Austin Design Center Email: javier.bruguera@arm.com Abstract—Digit-recurrence division is widely used in actual high-performance microprocessors because it presents a good …
Continue reading at www.ecs.umass.edu (PDF) (other versions)

Classifications

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    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
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