Chang et al., 1992 - Google Patents
Technology mapping via transformations of function graphsChang et al., 1992
View PDF- Document ID
- 621596673807437104
- Author
- Chang S
- Marek-Sadowska M
- Publication year
- Publication venue
- Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors
External Links
Snippet
Abstract Programmable Gate Arrays (PGAs) are important media for rapid system prototyping. The most popular architectures for PGAs are the table look up (TLU) and the multipleror based (MB) architectures. In this paper we address the problem of technology …
- 238000005516 engineering process 0 title abstract description 9
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
- G06F17/30943—Information retrieval; Database structures therefor; File system structures therefor details of database functions independent of the retrieved data type
- G06F17/30946—Information retrieval; Database structures therefor; File system structures therefor details of database functions independent of the retrieved data type indexing structures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computer systems based on biological models
- G06N3/12—Computer systems based on biological models using genetic models
- G06N3/126—Genetic algorithms, i.e. information processing using digital simulations of the genetic system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Chang et al. | Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams | |
Chang et al. | Technology mapping via transformations of function graphs | |
US5805462A (en) | Automatic synthesis of integrated circuits employing boolean decomposition | |
Cong et al. | An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs | |
Sangiovanni-Vincentelli et al. | Synthesis method for field programmable gate arrays | |
US5349659A (en) | Hierarchical ordering of logical elements in the canonical mapping of net lists | |
US7525457B2 (en) | Transforming design objects in a computer by converting data sets between data set types | |
US5787010A (en) | Enhanced dynamic programming method for technology mapping of combinational logic circuits | |
JPH08510885A (en) | Field programmable logic device that dynamically interconnects to a dynamic logic core | |
Ciesielski et al. | PLADE: A two-stage PLA decomposition | |
WO2001033441A2 (en) | Structural regularity extraction and floorplanning in datapath circuits using vectors | |
Kravets et al. | Constructive library-aware synthesis using symmetries | |
Debnath et al. | Multiple-valued minimization to optimize PLAs with output EXOR gates | |
Wurth et al. | Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs | |
Czajkowski et al. | Functionally linear decomposition and synthesis of logic circuits for FPGAs | |
Luba et al. | Evolutionary multi-level network synthesis in given design style | |
Jóźwiak et al. | Fast and compact sequential circuits for the FPGA-based reconfigurable systems | |
Crastes et al. | A technology mapping method based on perfect and semi-perfect matchings | |
Legl et al. | Computing support-minimal subfunctions during functional decomposition | |
Jacobi | A study of the application of binary decision diagrams in multilevel logic synthesis | |
Kung et al. | BDDMAP: A Technology Mapper Based on a New Covering Algorithm. | |
Cong et al. | An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. | |
Louie et al. | A digit-recurrence square root implementation for field programmable gate arrays | |
Ye | Field-programmable gate array architectures and algorithms optimized for implementing datapath circuits | |
Pedram et al. | Technology decomposition using optimal alphabetic trees |