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Keutzer et al., 1991 - Google Patents

Is redundancy necessary to reduce delay

Keutzer et al., 1991

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Document ID
5936224742385122289
Author
Keutzer K
Malik S
Saldanha A
Publication year
Publication venue
Proceedings of the 27th ACM/IEEE Design Automation Conference

External Links

Snippet

Logic optimization procedures principally attempt to optimize three criteria: performance, area and testability. The relationship between area optimization and testability has recently been explored. As to the relationship between performance and testability, experience has …
Continue reading at dl.acm.org (PDF) (other versions)

Classifications

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    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G06F17/5031—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
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