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Mrugalski et al., 2015 - Google Patents

A deterministic BIST scheme based on EDT-compressed test patterns

Mrugalski et al., 2015

Document ID
5812273650043881157
Author
Mrugalski G
Rajski J
Rybak Å
Solecki J
Tyszer J
Publication year
Publication venue
2015 IEEE International Test Conference (ITC)

External Links

Snippet

The paper presents a novel deterministic built-in self-test (BIST) scheme. The proposed solution seamlessly integrates with on-chip EDT-based decompression logic and takes advantage of two key observations:(1) specified positions of ATPG-produced test cubes are …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G01R31/317—Testing of digital circuits
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    • G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
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    • G—PHYSICS
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    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test

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