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Dimitrov et al., 2006 - Google Patents

Locality-based information redundancy for processor reliability

Dimitrov et al., 2006

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Document ID
5648833037948567514
Author
Dimitrov M
Zhou H
Publication year
Publication venue
WAR-2 workshop in conjunction with MICRO-39

External Links

Snippet

In this work, we propose a novel information redundancy scheme to protect microprocessors from transient faults. Similar to traditional information redundancy techniques such as ECC, our approach does not require redundant execution in order to detect faults. Instead …
Continue reading at hzhou.wordpress.ncsu.edu (PDF) (other versions)

Classifications

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    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • G06F9/3844Speculative instruction execution using dynamic prediction, e.g. branch history table
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    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
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    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

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