West, 1992 - Google Patents
Protocol validation—principles and applicationsWest, 1992
- Document ID
- 4683616395631941049
- Author
- West C
- Publication year
- Publication venue
- Computer Networks and ISDN Systems
External Links
Snippet
We describe two techniques that have been developed for automated protocol validation, reachability analysis and random walk validation. A number of case studies are presented in order to demonstrate how the techniques can be applied to protocols of varying complexity …
- 238000010200 validation analysis 0 abstract description 129
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
- H04L12/26—Monitoring arrangements; Testing arrangements
- H04L12/2697—Testing equipment; Routine testing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L29/00—Arrangements, apparatus, circuits or systems, not covered by a single one of groups H04L1/00 - H04L27/00 contains provisionally no documents
- H04L29/02—Communication control; Communication processing contains provisionally no documents
- H04L29/06—Communication control; Communication processing contains provisionally no documents characterised by a protocol
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Application independent communication protocol aspects or techniques in packet data networks
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—High level architectural aspects of 7-layer open systems interconnection [OSI] type protocol stacks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing packet switching networks
- H04L43/50—Testing arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance or administration or management of packet switching networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network-specific arrangements or communication protocols supporting networked applications
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Kristensen et al. | The practitioner’s guide to coloured Petri nets | |
Dahbura et al. | Formal methods for generating protocol conformance test sequences | |
Brand et al. | On communicating finite-state machines | |
Lee et al. | Conformance testing of protocols specified as communicating finite state machines-a guided random walk based approach | |
Alur et al. | Model checking of message sequence charts | |
Hartmann et al. | UML-based integration testing | |
Abdulla et al. | On-the-fly analysis of systems with unbounded, lossy FIFO channels | |
Holzmann | The model checker SPIN | |
US5659555A (en) | Method and apparatus for testing protocols | |
Babich et al. | Formal methods for specification and analysis of communication protocols | |
West | Protocol validation—principles and applications | |
Simons et al. | Mechanical verification of the IEEE 1394a root contention protocol using Uppaal2k | |
Sidhu et al. | Experience with formal methods in protocol development | |
Sunshine | Formal Modeling of Communication Protocols: State of the Art, October 1980 | |
Salaun et al. | Formal verification of CHP specifications with CADP illustration on an asynchronous network-on-chip | |
Özdemir et al. | Protocol validation by simultaneous reachability analysis | |
David et al. | Modelling and analysis of a commercial field bus protocol | |
US6516306B1 (en) | Model checking of message flow diagrams | |
Borrione et al. | A formal approach to the verification of networks on chip | |
Bochmann et al. | Test result analysis with respect to formal specifications | |
Sidhu et al. | Verification of NBS class 4 transport protocol | |
Ezust et al. | An automatic trace analysis tool generator for estelle specifications | |
Abdulla et al. | Channel Representations in Protocol Verification: Preliminary Version | |
Huang et al. | An incremental protocol verification method | |
Arts et al. | Global scheduler properties derived from local restrictions |