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Sanaullah et al., 2014 - Google Patents

Analysis of RLC interconnect delay model using second order approximation

Sanaullah et al., 2014

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Document ID
4308684350405922518
Author
Sanaullah M
Chowdhury M
Publication year
Publication venue
2014 IEEE International Symposium on Circuits and Systems (ISCAS)

External Links

Snippet

Continuous scaling of CMOS technology leads to extremely fast device. However, the resulting interconnect structures impose so much parasitic effects that the advantage of ultra- high-speed nanoscale transistors would be completely overshadowed if appropriate …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

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    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
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