Jones, 1991 - Google Patents
The reconfigurable application of ERASJones, 1991
- Document ID
- 4255866852682707234
- Author
- Jones G
- Publication year
- Publication venue
- IEE Colloquium on User-Configurable Logic-Technology and Applications
External Links
Snippet
Dynamic reconfiguration (ie the reprogramming of a device whilst in a working system) is a novel technique and its full exploitation is yet to come. By sharing silicon it makes possible savings in space and power consumption whilst removing some of the restrictions on adding …
- 238000000034 method 0 abstract description 3
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6265894B1 (en) | Reconfigurable integrated circuit with integrated debugging facilities for use in an emulation system | |
US5315178A (en) | IC which can be used as a programmable logic cell array or as a register file | |
EP0582660B1 (en) | Device and method for multiplexing pins for in-system programming | |
KR940000293B1 (en) | Simplified synchronous mesh processor | |
US6091263A (en) | Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM | |
US6717433B2 (en) | Reconfigurable integrated circuit with integrated debugging facilities and scalable programmable interconnect | |
US6020758A (en) | Partially reconfigurable programmable logic device | |
US5612633A (en) | Circuit for simultaneously inputting and outputting signals on a single wire | |
CA2313462C (en) | Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem | |
US6292018B1 (en) | Configurable cellular array | |
US5600597A (en) | Register protection structure for FPGA | |
US3924144A (en) | Method for testing logic chips and logic chips adapted therefor | |
US20030120974A1 (en) | Programable multi-port memory bist with compact microcode | |
US5386155A (en) | Apparatus and method for selecting polarity and output type in a programmable logic device | |
US6067615A (en) | Reconfigurable processor for executing successive function sequences in a processor operation | |
US6460131B1 (en) | FPGA input output buffer with registered tristate enable | |
US5847450A (en) | Microcontroller having an n-bit data bus width with less than n I/O pins | |
Shen et al. | A functional testing method for microprocessors | |
US4458163A (en) | Programmable architecture logic | |
JPH09198874A (en) | Random access memory array | |
US7954077B2 (en) | Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells | |
Jones | The reconfigurable application of ERAS | |
US7876125B1 (en) | Register data retention systems and methods during reprogramming of programmable logic devices | |
US6181158B1 (en) | Configuration logic to eliminate signal contention during reconfiguration | |
US5572198A (en) | Method and apparatus for routing in reduced switch matrices to provide one hundred percent coverage |