Kim et al., 1999 - Google Patents
Cell selection algorithm for the multiple input-queued ATM switch: Chessboard and Random cell selectionsKim et al., 1999
View PDF- Document ID
- 4218478492749860775
- Author
- Kim H
- Kim K
- Lee Y
- Yoon H
- Oh C
- Publication year
- Publication venue
- IEEE ATM Workshop'99 Proceedings (Cat. No. 99TH8462)
External Links
Snippet
A simple and efficient cell selection algorithm for the multiple input-queued ATM switch, named the chessboard cell selection algorithm, is proposed in this paper. The proposed algorithm selects one of the transmission requests for the output port with the lowest value of …
- 230000000903 blocking 0 abstract description 28
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5679—Arbitration or scheduling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5651—Priority, marking, classes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding through a switch fabric
- H04L49/253—Connections establishment or release between ports
- H04L49/254—Centralized controller, i.e. arbitration or scheduling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
- H04L49/1553—Interconnection of ATM switching modules, e.g. ATM switching fabrics
- H04L49/1561—Distribute and route fabrics, e.g. Batcher-Banyan
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding through a switch fabric
- H04L49/256—Routing or path finding in ATM switching fabrics
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Switching fabric construction
- H04L49/104—ATM switching fabrics
- H04L49/105—ATM switching elements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/50—Overload detection; Overload protection
- H04L49/505—Corrective Measures, e.g. backpressure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
- H04L49/1515—Non-blocking multistage, e.g. Clos
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Switching fabric construction
- H04L49/101—Crossbar or matrix
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/64—Distributing or queueing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services or operations
- H04L49/201—Multicast or broadcast
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Lee | A modular architecture for very large packet switches | |
| US6904047B2 (en) | Cell scheduling method of input and output buffered switch using simple iterative matching algorithm | |
| Bianco et al. | Frame-based matching algorithms for input-queued switches | |
| Schoenen et al. | Weighted arbitration algorithms with priorities for input-queued switches with 100% throughput | |
| Duan et al. | Matrix unit cell scheduler (MUCS) for input-buffered ATM switches | |
| Kleban et al. | CRRD-OG: A packet dispatching algorithm with open grants for three-stage buffered Clos-network switches | |
| Mekkittikul et al. | Scheduling VOQ switches under non-uniform traffic | |
| Kim et al. | Cell selection algorithm for the multiple input-queued ATM switch: Chessboard and Random cell selections | |
| Kim et al. | KSMINs: knockout switch-based multistage interconnection networks for high-speed packet switching | |
| Li et al. | Frame-based matching algorithms for optical switches | |
| Li et al. | Multi-path Self-routing Switching Structure; by Interconnection of Multistage Sorting Concentrators | |
| Cui et al. | A threshold based scheduling algorithm for input queue switch | |
| Baranowska et al. | The new packet scheduling algorithms for VOQ switches | |
| Lin et al. | Frame occupancy-based dispatching schemes for buffered three-stage Clos-network switches | |
| Radusinovic et al. | New round-robin scheduling algorithm for combined input-crosspoint buffered switch | |
| Minkenberg et al. | A robust switch architecture for bursty traffic | |
| Zheng et al. | An efficient round-robin algorithm for combined input-crosspoint-queued switches | |
| Nong et al. | Delay analysis of combined input-crosspoint queueing switches | |
| Lee et al. | A practical approach for statistical matching of output queueing | |
| Han et al. | Simple iterative matching for input and output buffered switch with multiple switching planes | |
| Baranowska et al. | Performance evaluation of the multiple output queueing switch under different traffic patterns | |
| Han et al. | Fast scheduling algorithm for input and output buffered ATM switch with multiple switching planes | |
| Song et al. | A simple and fast scheduler for input queued ATM switches | |
| Li et al. | QoS guaranteed input queued scheduling algorithms with low delay | |
| Wong et al. | A large scale packet switch interconnection architecture using overflow switches |