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Pimentel et al., 2016 - Google Patents

Hybrid hardware/software floating-point implementations for optimized area and throughput tradeoffs

Pimentel et al., 2016

View PDF
Document ID
4105584346255050195
Author
Pimentel J
Bohnenstiehl B
Baas B
Publication year
Publication venue
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

External Links

Snippet

Hybrid floating-point (FP) implementations improve software FP performance without incurring the area overhead of full hardware FP units. The proposed implementations are synthesized in 65-nm CMOS and integrated into small fixed-point processors with a RISC …
Continue reading at ieeexplore.ieee.org (PDF) (other versions)

Classifications

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