RISC-V: Lower Mulh, Mulhsu, Mulhu

Closes RV-635

What

Lowers opcode Mulh

Why

Part of the effort to enable internal opcodes to be runnable in both interpreted mode and jitted mode

How

Moved mulh* instruction logic from rv32m.rs to integer.rs and use them for both to_run and to_lowering

Added support for mul_high in icb for both interpreted and jitted mode

Splitted the Zero and non zero cases for the 3 opcodes

Renamed the opcode according to the opcode redesign

Manually Testing

make -C src/riscv all

Benchmarking

	master(interpreted)	This MR(interpreted)	master(outline jit)	This MR(outline jit)	Improvement(interpreted)	Improvement(outline jit)
M2 MBP	12.045 TPS	12.109 TPS	12.776 TPS	13.110 TPS	0.53%	2.61%
Benchmark Machine	7.536 TPS	7.634 TPS	8.856 TPS	9.039 TPS	1.30%	2.06%

Regressions

Regression is due to changing the 3 opcodes to take NonZeroXRegisters instead of XRegister by splitting on the zero case.

Tasks for the Author

• Link all Linear issues related to this MR using magic words (e.g. part of, relates to, closes).
• Eliminate dead code and other spurious artefacts introduced in your changes.
• Document new public functions, methods and types.
• Make sure the documentation for updated functions, methods, and types is correct.
• Add tests for bugs that have been fixed.
• Put in reasonable effort to ensure that CI will pass.
  • make -C src/riscv
  • dune build src/lib_riscv
  • dune build src/rust_deps
• Benchmark performance and populate the table above if needed.
• Explain changes to regression test captures when applicable.
• Write commit messages to reflect the changes they're about.
• Self-review your changes to ensure they are high-quality.
• Complete all of the above before assigning this MR to reviewers.