RISC-V: mark control flow instructions as uncacheable

Part of RV-172

What

Mark instructions that will not be allowed in the block cache as uncacheable.

Why

Allows the block execution to make certain assumptions about the instructions being executed as part of a block (namely, that executing such instructions will not result in either virtual->physical address mapping changing, nor interrupts being triggered).

Manually Testing

make -C src/riscv all

Benchmarking

Does not alter performance as measured on the benchmark machine.

Tasks for the Author

• Link all Linear issues related to this MR using magic words (e.g. part of, relates to, closes).
• Eliminate dead code and other spurious artefacts introduced in your changes.
• Document new public functions, methods and types.
• Make sure the documentation for updated functions, methods, and types is correct.
• Add tests for bugs that have been fixed.
• Put in reasonable effort to ensure that CI will pass.
• Benchmark performance and populate the table above if needed.
• Write commit messages to reflect the changes they're about.
• Self-review your changes to ensure they are high-quality.
• Complete all of the above before assigning this MR to reviewers.

/assign @ole.kruger
/assign @victor-dumitrescu
/assign @felix.puscasu1
/assign @anastasia.courtney
/assign @emturner

/assign_reviewer @ole.kruger
/assign_reviewer @victor-dumitrescu
/assign_reviewer @felix.puscasu1
/assign_reviewer @anastasia.courtney
/assign_reviewer @emturner

/unassign me
/unassign_reviewer me

/ready