RISC-V: dispatch run from opcode instead of instruction

• closes RV-300
• part of RV-179

What

Introduce a new instruction format - separating opcode vs arguments, as a replacement of IsntrCacheable used in caches.

Why

This comes with a small performance improvement, but unlocks a subsequent larger one by allowing the block cache to dispatch the called-functions at block construction, rather than at runtime. (see RISC-V: dispatch instr functions during block c... (!15597 - merged))

How

We introduce a new OpCode for all cacheable instructions, and the associated Args struct containing all possible arguments for these instructions.

We parse as before, but then convert an InstrCacheable into an Instruction before storing it in the cache.

Manually Testing

Since we no longer run InstrCacheable directly at all - we can be confident that the new instructions behave correctly through CI.

make -C src/riscv all

Benchmarking

	master	This MR	Improvement
AMD Ryzen 7 7840U	2.678 TPS	2.768 TPS	3.36%
Benchmark Machine	2.032 TPS	2.107 TPS	3.69%

Tasks for the Author

• Link all Linear issues related to this MR using magic words (e.g. part of, relates to, closes).
• Eliminate dead code and other spurious artefacts introduced in your changes.
• Document new public functions, methods and types.
• Make sure the documentation for updated functions, methods, and types is correct.
• Add tests for bugs that have been fixed.
• Put in reasonable effort to ensure that CI will pass.
• Benchmark performance and populate the table above if needed.
• Write commit messages to reflect the changes they're about.
• Self-review your changes to ensure they are high-quality.
• Complete all of the above before assigning this MR to reviewers.