Commits · master · Yiğit Süoğlu / Simple UART

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Aug 03, 2023
- added license info · cc3fa95b
  Yiğit Süoğlu authored Aug 03, 2023
  
  cc3fa95b
Feb 28, 2022
- add hw licences for ip hw · f79996f6
  Yiğit Süoğlu authored Feb 28, 2022
  
  f79996f6
Dec 01, 2021
- add full uart ip · a1e3b099
  Yiğit Süoğlu authored Nov 30, 2021
  
  a1e3b099
Nov 30, 2021
- remove shifts for status · 4c1557bd
  Yiğit Süoğlu authored Nov 30, 2021
  
  4c1557bd
- constructor with custom values · e9013204
  Yiğit Süoğlu authored Nov 30, 2021
  
  e9013204
Nov 25, 2021
- source list for iVerilog · 71f03df7
  Yiğit Süoğlu authored Nov 25, 2021
  
  71f03df7
- add receiver IP · ae9743a3
  Yiğit Süoğlu authored Nov 25, 2021
  
  ae9743a3
Nov 24, 2021
- put enums inside the class · 962a78b7
  Yiğit Süoğlu authored Nov 24, 2021
  
  962a78b7
Nov 20, 2021
- prevent enums defined multiple times + non-argument const only if defined + fix indentation · 06256af9
  Yiğit Süoğlu authored Nov 20, 2021
  
  06256af9
- Update comment header · e2285f04
  Yiğit Süoğlu authored Nov 20, 2021
  
  e2285f04
Nov 03, 2021
- add OxDEC0DEE3 for non existing addresses · fc1e95ca
  Yiğit Süoğlu authored Nov 03, 2021
  
  fc1e95ca
Oct 25, 2021
- small corrections · 39bada00
  Yiğit Süoğlu authored Oct 25, 2021
  
  39bada00
- update file groups · e7bc242a
  Yiğit Süoğlu authored Oct 25, 2021
  
  e7bc242a
- edit comments · 829eae02
  Yiğit Süoğlu authored Oct 25, 2021
  
  829eae02
Oct 24, 2021
- add some temp files + .Xil · 01148daf
  Yiğit Süoğlu authored Oct 24, 2021
  
  01148daf
- transmitter IP, first version · c3d03793
  Yiğit Süoğlu authored Oct 24, 2021
  
  c3d03793
Oct 21, 2021
- update test info · 63eab8d4
  Yiğit Süoğlu authored Oct 22, 2021
  
  63eab8d4
- extend frame err case · c48bc423
  Yiğit Süoğlu authored Oct 21, 2021
  
  c48bc423
- rm gated clks, add timescale · 62a9236a
  Yiğit Süoğlu authored Oct 21, 2021
  
  62a9236a
- update test codes · a3247c91
  Yiğit Süoğlu authored Oct 21, 2021
  
  a3247c91
- uart transmitter ip inital commit · a5f3c175
  Yiğit Süoğlu authored Oct 13, 2021
  
  a5f3c175
- only sysclk as a clk signal, rec waits rx to ready, add timescale · 167ff6a9
  Yiğit Süoğlu authored Oct 21, 2021
  
  167ff6a9
Oct 17, 2021
- bugfix: receiver doesn't shift data out in 7 bit · dd3f5b41
  Yiğit Süoğlu authored Oct 17, 2021
  
  dd3f5b41
Oct 12, 2021
- frame error detection + update tbs · 31f7d64a
  Yiğit Süoğlu authored Oct 12, 2021
  
  31f7d64a
- named association · 31874111
  Yiğit Süoğlu authored Oct 12, 2021
  
  31874111
- rename valid -> error_parity · 842a0051
  Yiğit Süoğlu authored Oct 12, 2021
  
  842a0051
Oct 11, 2021
- ch structure · 917b73b8
  Yiğit Süoğlu authored Oct 12, 2021
  
  917b73b8
- fix typos + ch structure · 73c96df0
  Yiğit Süoğlu authored Oct 12, 2021
  
  73c96df0
- ch coding style · 7d48420d
  Yiğit Süoğlu authored Oct 12, 2021
  
  7d48420d
May 23, 2021
- update test files · e0800800
  Yiğit Süoğlu authored May 23, 2021
  
  e0800800
- Clock module is seperated · dea65fa5
  Yiğit Süoğlu authored May 23, 2021
  
  dea65fa5
- vivado sim edits · 21c39d46
  Yiğit Süoğlu authored May 23, 2021
  
  21c39d46
- Update readme · 797f9645
  Yiğit Süoğlu authored May 23, 2021
  
  797f9645
Mar 22, 2021
- Add common baud rates into tables · db91dc3b
  Yiğit Süoğlu authored Mar 23, 2021
  
  db91dc3b
Jan 18, 2021
- edit dates · 1797685a
  Yiğit Süoğlu authored Jan 18, 2021
  
  1797685a
- sim stream · d28a5480
  Yiğit Süoğlu authored Jan 18, 2021
  
  d28a5480
- Redeclerations of uartClock in Tx and Rx rmvd · 323a592d
  Yiğit Süoğlu authored Jan 18, 2021
  
  323a592d
Dec 17, 2020
- github link fix · f035a93a
  Yiğit Süoğlu authored Dec 17, 2020
  
  f035a93a
- Test added · 56e12b38
  Yiğit Süoğlu authored Dec 17, 2020
  
  56e12b38
Dec 16, 2020
- Sim for Rx · 969a99ff
  Yiğit Süoğlu authored Dec 16, 2020
  
  969a99ff