Tags give the ability to mark specific points in history as being important
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pull-tcg-20250423
a3d40b5e · ·meson: Introduce top-level libuser_ss and libsystem_ss meson: Add hw_common_arch dictionary accel/tcg: Lots of cleanups to enable build once for: user-exec-stub.c, plugin-gen.c, translator.c page-vary: Restrict scope of TARGET_PAGE_BITS_MIN tcg: Always define TARGET_INSN_START_EXTRA_WORDS tcg: Convert TARGET_GUEST_DEFAULT_MO to TCGCPUOps::guest_default_memory_order tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field target/riscv: Do not expose rv128 CPU on user mode emulation -
pull-avr-20250422
eba24b60 · ·target/avr: Fix buffer read in avr_print_insn target/avr: Improve decode of LDS, STS target/avr: Move cpu register accesses into system memory target/avr: Increase TARGET_PAGE_BITS to 10
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pull-tcg-20250403
49551752 · ·tcg: Allocate TEMP_VAL_MEM frame in temp_load() tests/functional: Skip aarch64_replay test on macOS hw/arm: Do not build VMapple machine by default tests/functional/test_aarch64_rme_virt: fix sporadic failure
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pull-tcg-20250308
9e208076 · ·include/qemu: Tidy atomic128 headers. include/exec: Split out cpu-interrupt.h include/exec: Split many tlb_* declarations to cputlb.h include/accel/tcg: Split out getpc.h accel/tcg: system: Compile some files once linux-user/main: Allow setting tb-size
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pull-tcg-20250215-3
e726f658 · ·tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS tcg: Cleanups after disallowing 64-on-32 tcg: Introduce constraint for zero register tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2 linux-user: Move TARGET_SA_RESTORER out of generic/signal.h linux-user: Fix alignment when unmapping excess reservation target/sparc: Fix register selection for all F*TOx and FxTO* instructions target/sparc: Fix gdbstub incorrectly handling registers f32-f62 target/sparc: fake UltraSPARC T1 PCR and PIC registers -
pull-tcg-20250215-2
a39bdd0f · ·tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS tcg: Cleanups after disallowing 64-on-32 tcg: Introduce constraint for zero register tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2 linux-user: Move TARGET_SA_RESTORER out of generic/signal.h linux-user: Fix alignment when unmapping excess reservation target/sparc: Fix register selection for all F*TOx and FxTO* instructions target/sparc: Fix gdbstub incorrectly handling registers f32-f62 target/sparc: fake UltraSPARC T1 PCR and PIC registers -
pull-tcg-20250215
21327510 · ·tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS tcg: Cleanups after disallowing 64-on-32 tcg: Introduce constraint for zero register linux-user: Move TARGET_SA_RESTORER out of generic/signal.h linux-user: Fix alignment when unmapping excess reservation target/sparc: Fix register selection for all F*TOx and FxTO* instructions target/sparc: Fix gdbstub incorrectly handling registers f32-f62 target/sparc: fake UltraSPARC T1 PCR and PIC registers
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pull-tcg-20250117
db164982 · ·tcg: - Add TCGOP_TYPE, TCGOP_FLAGS. - Pass type and flags to tcg_op_supported, tcg_target_op_def. - Split out tcg-target-has.h and unexport from tcg.h. - Reorg constraint processing; constify TCGOpDef. - Make extract, sextract, deposit opcodes mandatory. - Merge ext{8,16,32}{s,u} opcodes into {s}extract. tcg/mips: Expand bswap unconditionally tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 tcg/riscv: Use BEXTI for single-bit extractions tcg/sparc64: Use SRA, SRL for {s}extract_i64 disas/riscv: Guard dec->cfg dereference for host disassemble util/cpuinfo-riscv: Detect Zbs accel/tcg: Call tcg_tb_insert() for one-insn TBs linux-user: Add missing /proc/cpuinfo fields for sparc -
pull-tcg-20241224
e4a8e093 · ·tcg/optimize: Remove in-flight mask data from OptContext fpu: Add float*_muladd_scalbn fpu: Remove float_muladd_halve_result fpu: Add float_round_nearest_even_max fpu: Add float_muladd_suppress_add_product_zero target/hexagon: Use float32_muladd accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core
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pull-tcg-20241212
7ac87b14 · ·tcg: Reset free_temps before tcg_optimize tcg/riscv: Fix StoreStore barrier generation include/exec: Introduce fpst alias in helper-head.h.inc target/sparc: Use memcpy() and remove memcpy32()
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pull-lu-20241122
d95fd983 · ·linux-user: Fix strace output for s390x mmap() linux-user: Print tid not pid with strace
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pull-tcg-20241116
8377e3fb · ·cpu: ensure we don't call start_exclusive from cpu_exec tcg: Allow top bit of SIMD_DATA_BITS to be set in simd_desc() accel/tcg: Fix user-only probe_access_internal plugin check linux-user: Fix setreuid and setregid to use direct syscalls linux-user: Tolerate CONFIG_LSM_MMAP_MIN_ADDR linux-user: Honor elf alignment when placing images linux-user/*: Reduce vdso alignment to 4k linux-user/arm: Select vdso for be8 and be32 modes
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pull-tcg-20241115
a020e0a8 · ·cpu: ensure we don't call start_exclusive from cpu_exec tcg: Allow top bit of SIMD_DATA_BITS to be set in simd_desc() accel/tcg: Fix user-only probe_access_internal plugin check linux-user: Fix setreuid and setregid to use direct syscalls linux-user: Tolerate CONFIG_LSM_MMAP_MIN_ADDR linux-user: Honor elf alignment when placing images linux-user/*: Reduce vdso alignment to 4k linux-user/arm: Select vdso for be8 and be32 modes
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pull-lu-20241105
6f58b090 · ·tests/tcg: Replace -mpower8-vector with -mcpu=power8 linux-user: Fix GDB complaining about system-supplied DSO string table index linux-user: Allow custom rt signal mappings
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pull-tcg-20241022
310df7a9 · ·tcg: Reset data_gen_ptr correctly tcg/riscv: Implement host vector support tcg/ppc: Fix tcg_out_rlw_rc target/i386: Walk NPT in guest real mode target/i386: Use probe_access_full_mmu in ptw_translate linux-user: Fix build failure caused by missing __u64 on musl linux-user: Emulate /proc/self/maps under mmap_lock linux-user/riscv: Fix definition of RISCV_HWPROBE_EXT_ZVFHMIN linux-user/ppc: Fix sigmask endianness issue in sigreturn
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pull-tcg-20241013
e530581e · ·linux-user/i386: Emulate orig_ax linux-user/vm86: Fix compilation with Clang tcg: remove singlestep_enabled from DisasContextBase accel/tcg: Add TCGCPUOps.tlb_fill_align target/hppa: Handle alignment faults in hppa_get_physical_address target/arm: Fix alignment fault priority in get_phys_addr_lpae
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pull-tcg-20241008
25f4e717 · ·linux-user: Fix parse_elf_properties GNU0_MAGIC check linux-user: Various improvements to strace linux-user: Add openat2 support linux-user/flatload: Take mmap_lock in load_flt_binary() accel/tcg: Make page_set_flags() documentation public tcg/ppc: Use TCG_REG_TMP2 for scratch tcg_out_qemu_st tcg/ppc: Use TCG_REG_TMP2 for scratch index in prepare_host_addr target/m68k: Always return a temporary from gen_lea_mode
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pull-tcg-20240922
c4d80fa6 · ·target/ppc: Fix lxvx/stxvx facility check linux-user: update syscall_nr.h to Linux v6.10 linux-user: update syscall.tbl to Linux v6.11 tcg: Fix iteration step in 32-bit gvec operation tcg: Propagate new TCGOp to add_as_label_use tcg/*: Do not expand cmp_vec, cmpsel_vec early tcg/optimize: Fold movcond with true and false values identical tcg/optimize: Optimize cmp_vec and cmpsel_vec tcg/optimize: Optimize bitsel_vec tcg/i386: Optimize cmpsel with constant 0 operand 3. tcg/i386: Implement cmp_vec with avx512 insns tcg/i386: Implement cmpsel_vec with avx512 insns tcg/i386: Implement vector TST{EQ,NE} for avx512 tcg/ppc: Implement cmpsel_vec and optimize with constant 0/-1 arguments tcg/s390x: Implement cmpsel_vec and optimize with constant 0/-1 arguments