Commits · pull-tcg-20210921 · Richard Henderson / QEMU · GitLab

Sep 22, 2021
- tcg/riscv: Remove add with zero on user-only memory access · 81c65ee2
  Richard Henderson authored Aug 05, 2021
  View commits for tag pull-tcg-20210921 pull-tcg-20210921
  81c65ee2
- hw/core: Make do_unaligned_access noreturn · fa947a66
  Richard Henderson authored Jul 29, 2021
  fa947a66
- tcg/sparc: Introduce tcg_out_mov_delay · 220b2da7
  Richard Henderson authored Aug 05, 2021
  220b2da7
- tcg/sparc: Drop inline markers · 897fd616
  Richard Henderson authored Aug 05, 2021
  897fd616
- tcg/mips: Drop special alignment for code_gen_buffer · 3d1e8ed0
  Richard Henderson authored Aug 06, 2021
  3d1e8ed0
- tcg/mips: Unset TCG_TARGET_HAS_direct_jump · 5a8f0a5d
  Richard Henderson authored Aug 06, 2021
  5a8f0a5d
- tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr · d7fc9f48
  Richard Henderson authored Aug 06, 2021
  d7fc9f48
- tcg/mips: Drop inline markers · 10d4af58
  Richard Henderson authored Aug 06, 2021
  10d4af58
- accel/tcg: Restrict cpu_handle_halt() to sysemu · 0596fa11
  Philippe Mathieu-Daudé authored Sep 12, 2021 and Richard Henderson committed Sep 21, 2021
  0596fa11
- include/exec: Move cpu_signal_handler declaration · 8b1d5b3c
  Richard Henderson authored Aug 03, 2021
  8b1d5b3c
Sep 21, 2021
- Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-20210921' into staging · 2c3e83f9
  Richard Henderson authored Sep 21, 2021
  2c3e83f9
- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210921' into staging · 81ceb36b
  Peter Maydell authored Sep 21, 2021
  81ceb36b
- target/arm: Optimize MVE 1op-immediate insns · 4b445c92
  Peter Maydell authored Sep 13, 2021
  4b445c92
- target/arm: Optimize MVE VSLI and VSRI · ce75c43f
  Peter Maydell authored Sep 13, 2021
  ce75c43f
- target/arm: Optimize MVE VSHLL and VMOVL · a7789fab
  Peter Maydell authored Sep 13, 2021
  a7789fab
- target/arm: Optimize MVE VSHL, VSHR immediate forms · 752970ef
  Peter Maydell authored Sep 13, 2021
  752970ef
- target/arm: Optimize MVE VMVN · 5cf525a8
  Peter Maydell authored Sep 13, 2021
  5cf525a8
- target/arm: Optimize MVE VDUP · f8d94803
  Peter Maydell authored Sep 13, 2021
  f8d94803
- target/arm: Optimize MVE VNEG, VABS · 4b1561c4
  Peter Maydell authored Sep 13, 2021
  4b1561c4
- target/arm: Optimize MVE arithmetic ops · bc3087f2
  Peter Maydell authored Sep 13, 2021
  bc3087f2
- target/arm: Optimize MVE logic ops · 451f9d66
  Peter Maydell authored Sep 13, 2021
  451f9d66
- target/arm: Add TB flag for "MVE insns not predicated" · 26702213
  Peter Maydell authored Sep 13, 2021
  26702213
- target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration · 85e7d1e9
  Peter Maydell authored Sep 13, 2021
  85e7d1e9
- target/arm: Avoid goto_tb if we're trying to exit to the main loop · 84848481
  Peter Maydell authored Sep 13, 2021
  84848481
- hvf: arm: Add rudimentary PMC support · dd43ac07
  Alexander Graf authored Sep 16, 2021 and Peter Maydell committed Sep 21, 2021
  dd43ac07
- arm: Add Hypervisor.framework build target · 844a06bb
  Alexander Graf authored Sep 16, 2021 and Peter Maydell committed Sep 21, 2021
  844a06bb
- hvf: arm: Implement PSCI handling · 2c9c0bf9
  Alexander Graf authored Sep 16, 2021 and Peter Maydell committed Sep 21, 2021
  2c9c0bf9
- hvf: arm: Implement -cpu host · 585df85e
  Peter Maydell authored Sep 20, 2021
  585df85e
- arm/hvf: Add a WFI handler · 219c101f
  Peter Collingbourne authored Sep 16, 2021 and Peter Maydell committed Sep 21, 2021
  219c101f
- Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210920' into staging · 1c81a38c
  Peter Maydell authored Sep 21, 2021
  1c81a38c
- hw/riscv: opentitan: Correct the USB Dev address · ed481d98
  Alistair Francis authored Sep 16, 2021
  ed481d98
- target/riscv: csr: Rename HCOUNTEREN_CY and friends · db70794e
  Bin Meng authored Sep 15, 2021
  db70794e
- target/riscv: Backup/restore mstatus.SD bit when virtual register swapped · c6013547
  Frank Chang authored Sep 14, 2021
  c6013547
Sep 20, 2021
- docs/system/riscv: sifive_u: Update U-Boot instructions · 758c07c9
  Bin Meng authored Sep 11, 2021
  758c07c9
- hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer · ae000c5f
  Frank Chang authored Sep 12, 2021
  ae000c5f
- hw/dma: sifive_pdma: allow non-multiple transaction size transactions · e22d90f5
  Green Wan authored Sep 12, 2021
  e22d90f5
- hw/dma: sifive_pdma: claim bit must be set before DMA transactions · 9a8c26c0
  Frank Chang authored Sep 12, 2021
  9a8c26c0
- hw/dma: sifive_pdma: reset Next* registers when Control.claim is set · de7c7988
  Frank Chang authored Sep 12, 2021
  de7c7988
- hw/riscv: virt: Add optional ACLINT support to virt machine · 954886ea
  Anup Patel authored Aug 31, 2021
  954886ea
- hw/riscv: virt: Re-factor FDT generation · 0ffc1a95
  Anup Patel authored Aug 31, 2021
  0ffc1a95