Commits · master · Joe Helmick / Arty01 · GitLab

Oct 26, 2020
- started RX code in VM · 746d92ef
  Joe Helmick authored Oct 26, 2020
  
  746d92ef
Oct 23, 2020
- didn't get threaded to work, but other UI and instructions coded. LIFE works.... · 25f31e61
  Joe Helmick authored Oct 23, 2020
  25f31e61
Sep 30, 2020
- major changes; some new instructions, tkinter debugger, vm, etc. · a76e99d3
  Joe Helmick authored Sep 30, 2020
  
  a76e99d3
Aug 09, 2020
- asm language changes; new instructions and aliases; · 55a71b84
  Joe Helmick authored Aug 09, 2020
  
  55a71b84
Jul 26, 2020
- some changes to language syntax · 9ff7667e
  Joe Helmick authored Jul 26, 2020
  
  9ff7667e
Jul 23, 2020
- Merge branch 'master' of https://gitlab.com/joe_helmick/arty01 · f84c0ff8
  Joe Helmick authored Jul 23, 2020
  
  f84c0ff8
- added RTL schematic · 6cb5097f
  Joe Helmick authored Jul 23, 2020
  
  6cb5097f
- Add README.md · 94a00128
  Joe Helmick authored Jul 23, 2020
  
  94a00128
- Add LICENSE · 9ccbc992
  Joe Helmick authored Jul 23, 2020
  
  9ccbc992
- WORKING. Life game works at 921,600 bps. Rev A of this project is done. · 26fd5f0e
  Joe Helmick authored Jul 23, 2020
  
  26fd5f0e
Jul 19, 2020
- working TX UART at 115200 bps · 4de7d68c
  Joe Helmick authored Jul 19, 2020
  
  4de7d68c
Jul 12, 2020
- fixed the io/strobe issue; changed to 64Mhz and timing passes; added some basic IO constraints · f982c3ba
  Joe Helmick authored Jul 12, 2020
  
  f982c3ba
Jul 11, 2020
- updated gitignre · bf127479
  Joe Helmick authored Jul 11, 2020
  
  bf127479
- annotated XDC file before scope testing; need implementation testbench · 9a07cc9f
  Joe Helmick authored Jul 11, 2020
  
  9a07cc9f
- meets timing at 48 MHz · ddf03d53
  Joe Helmick authored Jul 11, 2020
  
  ddf03d53
Jul 10, 2020
- reformulated divider to run off clock; still missing some timing but divider... · 36c88f99
  Joe Helmick authored Jul 10, 2020
  36c88f99
Jul 08, 2020
- commit before addressing timing issues, 0.000 required times? · 0de11e86
  Joe Helmick authored Jul 08, 2020
  
  0de11e86
Jul 05, 2020
- synth/impl at 48Mhz meets timing; next is cleanup and further simulation · 10aa4281
  Joe Helmick authored Jul 05, 2020
  
  10aa4281
Jul 03, 2020
- finish up commit to master after merge · e459f18b
  Joe Helmick authored Jul 03, 2020
  
  e459f18b
- got mul and div working; added many other instructions; runs great in simulation now · caf9a41e
  Joe Helmick authored Jul 03, 2020
  
  caf9a41e
Jun 27, 2020
- changed fsm, but added other registered drivers to remove synth errors; still... · 89946230
  Joe Helmick authored Jun 27, 2020
  89946230
Jun 23, 2020
- regfile works; many but not all instructions tested; fails timing; need to fix poor FSM model; · 9c09bd9a
  Joe Helmick authored Jun 23, 2020
  
  9c09bd9a
Jun 21, 2020
- all on clk_cpu now · 6a115a81
  Joe Helmick authored Jun 21, 2020
  
  6a115a81
- main FSM running off clk_cpu now; still some stuff warned as inferred latches; · fccbbb66
  Joe Helmick authored Jun 21, 2020
  
  fccbbb66
- small comment on the reset source · 96f08e51
  Joe Helmick authored Jun 21, 2020
  
  96f08e51
- CLKGEN created; simulation running with generated clocks · 07ab6ae0
  Joe Helmick authored Jun 21, 2020
  
  07ab6ae0
- got the CLKGEN module working; generated clocks showing in simulation · cf8d0580
  Joe Helmick authored Jun 21, 2020
  
  cf8d0580
Jun 20, 2020
- fixed make(); fixed JAZ JANZ RETZ RETNZ instructions; · c663c32f
  Joe Helmick authored Jun 20, 2020
  
  c663c32f
- simulation shows divide instruction working; need to convert make_0 to make(); · 76d91a1d
  Joe Helmick authored Jun 20, 2020
  
  76d91a1d
- simulation shows divide instruction working; need to convert make_0 to make(); · 06623541
  Joe Helmick authored Jun 20, 2020
  
  06623541
Jun 18, 2020
- initial commit of migrated project; assembler included; some additional math instructions added; · db58fb36
  Joe Helmick authored Jun 18, 2020
  
  db58fb36