V

verilog

Wafer.space tapeout of the classic Z80 8-bit CPU using Global Foundry 180 nm (gf180mcu) process.

Tapeout repository: https://github.com/rejunity/ws0-z80-open-silicon-gf180mcu

Project repository: https://github.com/rejunity/z80-open-silicon

Toolchain for simulating and building FPGA projects.

Running legacy Xilinx ISE FPGA software on a MacOS system (including Apple Silicon) using Docker.

Collection of utility modules written in Verilog

Verible build container.

Verible build container.

Welcome to the repository for the VALE8x64 project.

The soft core for the Ice Sea VR headset. Designed to be run on the FPGA of the headset mainboard

Implementation of Intel8080 cpu written in verilog running spaceinvaders.

Final project for the MSc course of Laboratory of Advanced Electronics held in 2021 by Prof. Leonardo Ricci at the University of Trento.

Webpage: http://wilferciro.gitlab.io/sintel Documentation: https://sintel.readthedocs.io/en/latest/

Set of simple modules to communicate via UART

Set of simple modules to communicate via SPI protocol.

Simple I²S Master

Set of simple modules to communicate via I²C Bus.

An implementation of Simon Says in Verilog for Xilinx FPGA systems

Pair of modules to calculate crc values sequentially

RISC-Y: RISC-V-Inspired Siple Computer for You

A basic RV32I core for practice.