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Commits · master
qemu
Browse files
Oct 07, 2025
Merge tag 'pull-10.2-maintainer-071025-1' of
https://gitlab.com/stsquad/qemu
into staging
· 37ad0e48
Richard Henderson
authored
Oct 07, 2025
37ad0e48
Merge tag 'physmem-20251007' of
https://github.com/philmd/qemu
into staging
· 637a8b25
Richard Henderson
authored
Oct 07, 2025
637a8b25
Merge tag 'pull-target-arm-20251007' of
https://gitlab.com/pm215/qemu
into staging
· 40e62b90
Richard Henderson
authored
Oct 07, 2025
40e62b90
target/arm: Enable FEAT_RME_GPC2 for -cpu max with x-rme
· 932cac41
Richard Henderson
authored
Sep 25, 2025
and
Peter Maydell
committed
Oct 07, 2025
932cac41
target/arm: Implement APPSAA
· 663f9c25
Richard Henderson
authored
Sep 25, 2025
and
Peter Maydell
committed
Oct 07, 2025
663f9c25
target/arm: Fix GPT fault type for address outside PPS
· a0f1bb0d
Richard Henderson
authored
Sep 25, 2025
and
Peter Maydell
committed
Oct 07, 2025
a0f1bb0d
target/arm: Implement SPAD, NSPAD, RLPAD
· 59bcd13b
Richard Henderson
authored
Sep 25, 2025
and
Peter Maydell
committed
Oct 07, 2025
59bcd13b
target/arm: Implement GPT_NonSecureOnly
· ee45f4b4
Richard Henderson
authored
Sep 25, 2025
and
Peter Maydell
committed
Oct 07, 2025
ee45f4b4
target/arm: GPT_Secure is reserved without FEAT_SEL2
· 11dee1cb
Richard Henderson
authored
Sep 25, 2025
and
Peter Maydell
committed
Oct 07, 2025
11dee1cb
target/arm: Add cur_space to S1Translate
· bd08319b
Richard Henderson
authored
Sep 25, 2025
and
Peter Maydell
committed
Oct 07, 2025
bd08319b
target/arm: Enable FEAT_RME_GPC2 bits in gpccr_write
· af95e2aa
Richard Henderson
authored
Sep 25, 2025
and
Peter Maydell
committed
Oct 07, 2025
af95e2aa
target/arm: Add GPCCR fields from ARM revision L.b
· e2c25b12
Richard Henderson
authored
Sep 25, 2025
and
Peter Maydell
committed
Oct 07, 2025
e2c25b12
target/arm: Add isar feature test for FEAT_RME_GPC2
· 0407192a
Richard Henderson
authored
Sep 25, 2025
and
Peter Maydell
committed
Oct 07, 2025
0407192a
hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' header
· cedbe3b2
Philippe Mathieu-Daudé
authored
Oct 01, 2025
and
Peter Maydell
committed
Oct 07, 2025
cedbe3b2
hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5
· e836211f
Frederic Konrad
authored
Sep 30, 2025
and
Peter Maydell
committed
Oct 07, 2025
e836211f
hw/arm/xlnx-zynqmp: introduce helper to compute RPU number
· f51ad362
Clément "Helflym" Chigot
authored
Sep 30, 2025
and
Peter Maydell
committed
Oct 07, 2025
f51ad362
hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in header
· b94246a2
Clément "Helflym" Chigot
authored
Sep 30, 2025
and
Peter Maydell
committed
Oct 07, 2025
b94246a2
tests/functional/test_aarch64_xlnx_versal: test the versal2 machine
· f1924af1
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
f1924af1
hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine
· 3429cdd8
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
3429cdd8
docs/system/arm/xlnx-versal-virt: add a note about dumpdtb
· 39cf696f
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
39cf696f
docs/system/arm/xlnx-versal-virt: update supported devices
· 0ec8c429
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
0ec8c429
hw/arm/xlnx-versal-virt: tidy up
· e2e9b9e1
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
e2e9b9e1
hw/arm/xlnx-versal-virt: split into base/concrete classes
· ea7028b8
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
ea7028b8
hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt
· 84a759c3
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
84a759c3
hw/arm/xlnx-versal: add versal2 SoC
· 8cd160dc
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
8cd160dc
target/arm/tcg/cpu64: add the cortex-a78ae CPU
· 0252b88c
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
0252b88c
hw/arm/xlnx-versal: add the target field in IRQ descriptor
· 16aa53c9
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
16aa53c9
hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMap
· 268f7a3d
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
268f7a3d
hw/misc/xlnx-versal-crl: add the versal2 version
· 00580a9d
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
00580a9d
hw/arm/xlnx-versal: tidy up
· 4707024b
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
4707024b
hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices
· 48111f7e
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
48111f7e
hw/arm/xlnx-versal: reconnect the CRL to the other devices
· 9401022b
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
9401022b
hw/misc/xlnx-versal-crl: refactor device reset logic
· ff789d15
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
ff789d15
hw/misc/xlnx-versal-crl: split into base/concrete classes
· c27ca572
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
c27ca572
hw/misc/xlnx-versal-crl: remove unnecessary include directives
· 3074e351
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
3074e351
hw/arm/xlnx-versal: add the versal_get_num_cpu accessor
· 87830c4d
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
87830c4d
hw/arm/xlnx-versal: ddr: refactor creation
· e4a9bc0a
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
e4a9bc0a
hw/arm/xlnx-versal: ocm: refactor creation
· cf8f12b6
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
cf8f12b6
hw/arm/xlnx-versal: rpu: refactor creation
· 805bdea0
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
805bdea0
hw/arm/xlnx-versal: add support for GICv2
· 0dfff625
Luc Michel
authored
Sep 26, 2025
and
Peter Maydell
committed
Oct 07, 2025
0dfff625
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