Michiel Boland

Works for me

8580 BP/LP completely silent when cutoff is set to 0 or 1

I tried the crt image on 8565R2, 6569R1 and 6569R5 and they all have the same color (red). The code that triggers badline is [...] .C:80e0 A9 1B LDA #$1B .C:80e2 A0 1C LDY #$1C .C:80e4 A2 33 LDX #$33 .C:80e6 EC 12 D0 CPX $D012 .C:80e9 D0 FB BNE $80E6 .C:80eb 8C 11 D0 STY $D011 .C:80ee 8D 11 D0 STA $D011 ; badline here .C:80f1 A2 3A LDX #$3A ; next instruction is $A2 Since the next instruction is $A2 the color will be red. If you run the crt in vice you can change the colors by going into the monitor,...

VSP: wrong color in 3 "BA low" cycles when executed from cartridge

Interlace crash appears to be fixed in 3.7

xvic NTSC crashes when enabling interlace mode

The buffer is not a shift register. It is essentially a 40 word by 12 bit SRAM; there is circuit on the VIC chip that turns on each word line in sequence. The circuit is turned on when a bad line condition is activated. If you time it just right you can trigger a badline via VSP and then again a badline on the beginning of the following line. This will cause two word lines to be activated, where the distance of the word lines is determined by the time in between the two badline pulses. The behaviour...

There is a race condition in the VIC-II chip. When the horizontal counter is at 356 ($164) the first data byte for sprite 0 is fetched. This can be made to happen at the same time that the shift register for the sprite is being shifted, for example by placing the sprite 2 pixels earlier at X=354. The effect will be that whatever was in bit 7 of the data bus at the previous cycle will race the sprite's 'next' pixel. This is normally not relevant but the next pixel value is used when the sprite is...